This paper proposes a new methodology to design highly-balanced and highly-reliable front-end controllable clock tree,and solves the problem that clock tree has to be designed iteratively until performance and power dissipation requirements are met in back-end flow.
提出一种新的高平衡、高可靠性的前端可控时钟树设计方法,解决时钟树需要在后端工具中多次反复以达到满足性能和功耗要求的问题。
The equivalent checking in the formal verification was through the whole of digital circuit back-end design, such as: the comparison between RTL and netlist; the one between netlist and layout.
其中形式验证中的等价性检查贯穿于整个后端设计流程之中。
